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S3C821A/P821A
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLES
Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: -- Efficient register-oriented architecture -- Selectable CPU clock sources -- Idle and Stop power-down mode release by interrupt -- Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to specific interrupt levels.
S3C821A/P821A MICROCONTROLLER
The S3C821A/P821A single-chip CMOS microcontroller is fabricated using the highly advanced CMOS process, based on Samsung's newest CPU architecture. The S3C821A is a microcontroller with a 48-Kbyte mask-programmable ROM embedded. The S3P821A is a microcontroller with a 48-Kbyte one-time-programmable ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3C821A/P821A by integrating the following peripheral modules with the powerful SAM8 core: -- Six programmable I/O ports, including five 8-bit ports and one 7-bit port, for a total of 47 pins. -- Twelve bit-programmable pins for external interrupts. -- One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset). -- One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. -- Watch timer for real time. -- 4-input A/D converter -- Serial I/O interface The S3C821A/P821A is versatile microcontroller for cordless phone, pager, etc. They are currently available in 80-pin TQFP and 80-pin QFP package.
OTP
The S3P821A is an OTP (One Time Programmable) version of the S3C821A microcontroller. The S3P821A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of a masked ROM. The S3P821A is comparable to the S3C821A, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C821A/P821A
FEATURES
CPU * SAM8 CPU core LCD Controller/Driver * * Memory * * Data memory: 1040-byte of internal register file (Excluding LCD RAM) Program memory: 48-Kbyte internal program memory (ROM) * * * Up to 32 segment pins 3, 4, and 8 common selectable Choice of duty cycle All dots can be switched on/off Internal resistor circuit for LCD bias
Serial Port External Interface * 64-Kbyte external data memory area A/D Converter Instruction Execution Time * * 750 ns at 8 MHz (minimum, Main oscillator) 183 s at 32,768 Hz (minimum, Sub oscillator) * * 8-bit conversion resolution x 4 channel 34 s conversion time (4 MHz CPU clock, fxx/4) * One synchronous SIO
Oscillation Sources * * * * Crystal, ceramic, or RC for main system clock Crystal or external oscillator for subsystem clock Main system clock frequency: 8 MHz Subsystem clock frequency: 32.768 kHz
Interrupts * * * 7 interrupt levels and 19 interrupt sources 19 vectors Fast interrupt processing feature (for one selected interrupt level)
Power-down Modes I/O Ports * Five 8-bit I/O ports (P0-P4) and one 7-bit I/O port (P5) for a total of 47 bit-programmable pins * * * 8-Bit Basic Timer * One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function Operating Temperature Range * - 40 C to + 85 C Main idle mode (only CPU clock stops) Sub idle mode Stop mode (main/sub system oscillation stops)
Operating Voltage Range Watch Timer * * * Time internal generation: 3.91 ms, 0.5 s at 32,768 Hz Four frequency outputs to BUZ pin Clock source generation for LCD Package Type * Timers and Timer/Counters * * One 8-bit timer/counter (Timer 0) with three operating modes: Interval, Capture, and PWM One 16-bit timer/counter (Timer 1) with two 8-bit timer/counter modes 80-pin TQFP, 80-pin QFP * * 2.0 V to 5.5 V at 32 kHz (sub clock)-6 MHz (main clock) 2.2 V to 5.5 V at 8 MHz
1-2
S3C821A/P821A
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7
P1.0-P1.7
P2.0-P2.7
RESET
PORT 0
PORT 1
PORT 2
INTERNAL BUS XIN XOUT MAIN OSC I/O PORT and INTERRUPT CONTROL XIN XOUT SUB OSC PORT 4 P4.0-P4.7 PORT 3 P3.0-P3.7
T1CK TA TB
TIMER 1 A and B
SAM8 CPU
T0CK T0/T0CAP/ T0PWM
TIMER 0 48-KB ROM 1-KBYTE REGISTER FILE
PORT 5
P5.0-P5.6
SCK SI SO
SIO
LCD DRIVER
COM0-COM3 SEG0-SEG3/ COM4-COM7 SEG4-SEG31 VLC1
AVSS AVREF
A/D CONVERTER
VDD1 (INTERNAL) VSS 1 (INTERNAL) VDD2 (EXTERNAL) VSS2 (EXTERNAL)
WATCH TIMER
BUZ
ADC0-ADC3
Figure 1-1. S3C821A Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C821A/P821A
PIN ASSIGNMENTS
P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 P2.0/AS P2.1/DR VDD1(INT) VSS1 XOUT XIN TEST XTIN XTOUT RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P1.0/SEG24/AD0 P0.7/SEG23/A15 P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5
S3C821A
(80-TQFP)
SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11
Figure 1-2. S3C821A Pin Assignments (80-TQFP-1212)
1-4
P2.5/INT1/T1CK P2.6/INT2/TA P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8 P4.5/INT9 P4.6/INT10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S3C821A/P821A
PRODUCT OVERVIEW
P0.7/SEG23/A15 P1.0/SEG24/AD0 P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 P2.0/AS P2.1/DR VDD1(INT) VSS1 XOUT XIN TEST XTIN XTOUT RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK P2.5/INT1/T1CK P2.6/INT2/TA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7
S3C821A
(80-QFP)
SEG6 SEG5 SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11 P4.6/INT10 P4.5/INT9
Figure 1-3. S3C821A Pin Assignments (80-QFP-1420C)
P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1-5
PRODUCT OVERVIEW
S3C821A/P821A
PIN DESCRIPTIONS
Table 1-1. S3C821A Pin Descriptions Pin Names P0.0-P0.7 Pin Type I/O Pin Description 4-bit-programmable I/O port. Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are automatically disabled for output pins. Configurable as LCD segments/ external interface address and data lines 4-bit-programmable I/O port. Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are automatically disabled for output pins. Configurable as LCD segments/ external interface address and data lines 1-bit-programmable I/O port. Pull-up resistors are software assignable, and automatically disabled for output pins. P2.0-P2.3 can alternately be used as external interface lines. P2.4-P2.7 are configurable as alternate functions or external interrupts at falling edge with noise filters. 1-bit-programmable I/O port. Pull-up resistors are software assignable, and automatically disabled for output pins. P3.0-P3.3 can alternately be used as ADC. P3.7 is configurable as an alternate function. 1-bit-programmable I/O port. Pull-up resistors and open-drain outputs are software assignable. Pull-up resistors are automatically disabled for output pins. P4.0-P4.7 are configurable as external interrupts at a selectable edge with noise filters. 1-bit-programmable I/O port. Pull-up resistors are software assignable, and automatically disabled for output pins. P5.0-P5.3 are configurable as alternate functions. If SCK and SI are used as input, these pins have noise filters. Circuit Type H-32 Pin Numbers (note) 72-79 (74-80, 1) Share Pins SEG16/A8 - SEG23/A15
P1.0-1.7
I/O
H-32
80, 1-7 (2-9)
SEG24/AD0 - SEG31/AD7
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0-P3.3
I/O
D-4
8 (10) 9 (11) 18 (20) 19 (21) 20 (22) 21 (23) 22 (24) 23 (25) 25-28 (27-30) 30-32 (32-34) 33 (35) 34-41 (36-43)
AS DR DW DM INT0/T0CK INT1/T1CK INT2/TA INT3/TB ADC0-ADC3
I/O
F-16
P3.4-P3.6
D-4
P3.7 P4.0-P4.7 I/O
D-4 E-4
T0/T0PWM/ T0CAP INT4-INT11
P5.0 P5.1 P5.2 P5.3 P5.4-P5.6
I/O
D-4
42 (44) 43 (45) 44 (46) 45 (47) 46-48 (48-50)
SCK SI SO BUZ
NOTE: Parentheses indicate pin number for 80-QFP package.
1-6
S3C821A/P821A
PRODUCT OVERVIEW
Table 1-1. S3C821A Pin Descriptions (Continued) Pin Names VSS1, VDD1 XOUT, XIN TEST XTIN, XTOUT RESET INT0-INT3 T0CK T1CK TA TB T0 T0PWM T0CAP ADC0-ADC3 AVREF, AVSS INT4-INT11 BUZ SCK, SI, SO VLC1 VSS2, VDD2 COM0-COM3 SEG0-SEG3 (COM4-COM7) SEG4-SEG15 Pin Type -
- - -
Pin Description Power input pins for internal power block Main oscillator pins Chip test input pin Hold GND when the device is operating Sub oscillator pins for sub-system clock RESET signal input pin. Schmitt trigger input with internal pull-up resistor. External interrupts input with noise filter. 8Bit Timer 0 external clock input. Timer 1/A external clock input. Timer 1/A clock output Timer B clock output Timer 0 clock output Timer 0 PWM output Timer 0 capture input Analog input pins for A/D converts module A/D converter reference voltage and ground External interrupts input with noise filter. Buzzer signal output Serial clock, serial data input, serial data output LCD bias voltage input pins Power input pins for external power block LCD Common signal output LCD Common or Segment signal output LCD segment signal output
Circuit Type - - - - B D-4 D-4 D-4 D-4 D-4 D-4 D-4 D-4 F-16 - E-4 D-4 D-4 - - H-30 H-31 H-29
Pin Numbers (note) 10, 11 (12, 13) 12, 13 (14, 15) 14 (16) 15, 16 (17,18) 17 (19) 20-23 (22-25) 20 (22) 21 (23) 22 (24) 23 (25) 33 (35) 33 (35) 33 (35) 25-28 (27-30) 24, 29 (26, 31) 34-41 (36-43) 45 (47) 42-44 (44-46) 49 (51) 50, 51 (52, 53) 52-55 (54-57) 56-59 (58-61) 60-71 (62-73)
Share Pins - - - - - P2.4-P2.7 P2.4 P2.5 P2.6 P2.7 P3.7 P3.7 P3.7 P3.0-P3.3 - P4.0-P4.7 P5.3 P5.0-P5.2 - - - - -
I I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O - - O O O
NOTE: Parentheses indicate pin number for 80-QFP package.
1-7
PRODUCT OVERVIEW
S3C821A/P821A
Table 1-1. S3C821A Pin Descriptions (Continued) Pin Names SEG16- SEG23 SEG24- SEG31 A8-A15 AD0-AD7 AS DR DW DM Pin Type I/O I/O I/O I/O I/O I/O I/O I/O Pin Description LCD segment signal output LCD segment signal output External interface address lines External interface address/data lines Address strobe Data read Data write Data memory select Circuit Type H-32 H-32 H-32 H-32 D-4 D-4 D-4 D-4
Pin Numbers
Share Pins P0.0-P0.7 P1.0-P1.7 P0.0-P0.7 P1.0-P1.7 P2.0 P2.1 P2.2 P2.3
72-79 (74-80, 1) 80, 1-7 (2-9) 72-79 (74-80, 1) 80, 1-7 (2-9) 8 (10) 9 (11) 18 (20) 19 (21)
NOTE: Parentheses indicate pin number for 80-QFP package.
1-8
S3C821A/P821A
PRODUCT OVERVIEW
PIN CIRCUITS
VDD
DATA
VDD
P-CHANNEL
OUTPUT
INPUT N-CHANNEL
OUTPUT DISABLE
VSS
Figure 1-4. Pin Circuit Type A
Figure 1-6. Pin Circuit Type C
VDD
VDD
PULL-UP RESISTOR PULL-UP ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C
I/O
RESET
Noise Filter
SCHMITT TRIGER
Figure 1-5. Pin Circuit Type B
Figure 1-7. Pin Circuit Type D-4
1-9
PRODUCT OVERVIEW
S3C821A/P821A
VDD
PULL-UP RESISTOR PULL-UP ENABLE
VDD
OPEN-DRAIN EN
DATA OUTPUT DISABLE
I/O
VSS
Figure 1-8. Pin Circuit Type E-4
VDD
PULL-UP ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE C
I/O
ADEN ADSELECT DATA
T0 ADC
Figure 1-9. Pin Circuit Type F-16
1-10
S3C821A/P821A
PRODUCT OVERVIEW
VLC1
VLC1
VLC2 VLC3
VLC3 OUTPUT VLC4
VLC4
OUTPUT
VSS
VLC5
VSS
Figure 1-10. Pin Circuit Type H-29
Figure 1-12. Pin Circuit Type H-31
VLC1
VLC2 OUTPUT VLC5
VSS
Figure 1-11. Pin Circuit Type H-30
1-11
PRODUCT OVERVIEW
S3C821A/P821A
VDD PULL-UP RESISTOR V DD OPEN-DRAIN EN PULL-UP ENABLE I/O
DATA
LCD OUT EN
V SS
SEG OUTPUT DISABLE
CIRCUIT TYPE H-29
Figure 1-13. Pin Circuit Type H-32
1-12
S3C821A/P821A
ELECTRICAL DATA
17
OVERVIEW
ELECTRICAL DATA
In this section, S3C821A electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a Reset -- I/O capacitance -- A.C. electrical characteristics -- A/D converter electrical characteristics -- Input timing for external interrupts (P4, P2.4-P2.7) -- Input timing for RESET -- Serial data transfer timing -- Oscillation characteristics -- Oscillation stabilization time -- Operating voltage range
17-1
ELECTRICAL DATA
S3C821A/P821A
Table 17-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VIN VO I OH I OL One I/O port active All I/O ports active Output current Low One I/O port active All I/O ports - Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 (peak value) + 15 (note) Ports 0, 1, 2, and 3 Ports 4 and 5 Operating temperature Storage temperature TA TSTG - -
Duty .
Unit V V V mA
mA
+ 100 (peak value) + 60 (note) + 100 (peak value) + 60 (note) - 40 to + 85 - 65 to + 150
C C
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value x
17-2
S3C821A/P821A
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Operating Voltage Symbol VDD Conditions f OSC = 8 MHz (Instruction clock = 1.33 MHz) f OSC = 6 MHz (Instruction clock = 1 MHz) Input High voltage VIH1 VIH2 VIH3 Input Low voltage VIL1 VIL2 VIL3 Output High voltage Output Low voltage Input High leakage current VOH VOL ILIH1 P0 and P1 RESET, P2, P3, P4, and P5 XIN, XTIN P0 and P1 RESET, P2, P3, P4, and P5 XIN, XTIN VDD = 3 V; IOH = - 200 A All output pins VDD = 3 V; IOL= 1 mA All output pins VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT, XTIN, and XTOUT VIN = 0 V All input pins except those specified below for ILIL2 and RESET VIN = 0 V XIN, XOUT, XTIN, and XTOUT VOUT = VDD All output pins VOUT = 0 V All output pins VDD = 2.7 V to 5.5 V - 15 A per common pin VLCD = 2.7 V to 5.5 V - 15 A per segment pin - - - - - - - - VDD - 1.0 - - - 0.4 - Min 2.2 2.0 0.7 VDD 0.8 VDD VDD - 0.1 0 - - VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - 1.0 1 A V Typ - Max 5.5 Unit V
ILIH2 Input Low leakage current ILIL1
20 -1
ILIL2 Output High leakage current Output Low leakage current |VDD-COMi| voltage drop (i = 0-7) |VDD-SEGx| voltage drop (x = 0-31) ILOH ILOL VDC
- 20 1 -1 120 mV
VDS
-
-
120
17-3
ELECTRICAL DATA
S3C821A/P821A
Table 17-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter VLC2 output voltage VLC3 output voltage VLC4 output voltage VLC5 output voltage Pull-up resistors Symbol VLC2 VLC3 VLC4 VLC5 RL1 RL2 VIN = 0 V; TA = 25 C VDD = 3.0 10 %; Ports 0-5 VIN = 0 V; TA = 25 C VDD = 3.0 10 % Conditions VDD = 2.7 V to 5.5 V LCD clock = 0 Hz VLC1 = VDD Min 0.8 VDD - 0.15 0.6 VDD - 0.15 0.4 VDD - 0.15 0.2 VDD - 0.15 30 200 Typ 0.8 VDD 0.6 VDD 0.4 VDD 0.2 VDD 80 450 Max 0.8 VDD + 0.15 0.6 VDD + 0.15 0.4 VDD + 0.15 0.2 VDD + 0.15 200 800 Unit V
k
LCD voltage dividing resistor Supply current
(note)
RLCD IDD1
RESET only VLCD = 2.7 V to 5.5 V TA = 25 C Run mode; VDD=5.0V10% Crystal oscillator C1 = C2 = 22 pF VDD = 3.0 V 10 % 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz
45 -
65 6.0 4.5 2.9 2.0 1.3 1.2 0.6 0.4 20 7 0.5 0.3
80 12 9.0 5.8 4.0 2.6 2.4 1.2 0.8 40 14 3 2
k mA
IDD2
Idle mode; VDD=5.0 V 0 % Crystal oscillator C1 = C2 = 22 pF VDD = 3.0 V 10 %
6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz
IDD3 IDD4 IDD5
Run mode; VDD = 3.0 V 10 % 32 kHz crystal oscillator Idle mode; VDD = 3.0 V 10 % 32 kHz crystal oscillator Stop mode; VDD = 5.0 V 10 % Stop mode; VDD = 3.0 V 10 %
A
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops.
17-4
S3C821A/P821A
ELECTRICAL DATA
Table 17-3. Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Oscillator stabilization wait time Symbol VDDDR IDDDR tWAIT Conditions - VDDDR = 1.0 V Stop mode Released by RESET Released by interrupt Min 2.2 - - - Typ - - 216/fx (1)
(2)
Max 3.4 1 - -
Unit V A ms
NOTES: 1. fx is the main oscillator frequency.
2. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.
IDLE MODE (Basic Timer active)
~ ~
STOP MODE DATA RETENTION MODE
VDD
~ ~
NORMAL OPERATING MODE
V DDDR
EXECUTION OF STOP INSTRUCTION
0.8 V DD
Interrupt Request
t WAIT
Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt
17-5
ELECTRICAL DATA
S3C821A/P821A
RESET OCCURS
OSCILLATION STABILIZATION TIME NORMAL OPERATING MODE
~ ~
STOP MODE DATA RETENTION MODE
VDD
~ ~
VDDDR EXECUTION OF STOP INSTRUCTION RESET 0.2 V DD t WAIT 0.8 VDD
Figure 17-2. Stop Mode Release Timing When Initiated by a RESET
17-6
S3C821A/P821A
ELECTRICAL DATA
Table 17-4. Input/output Capacitance (TA = - 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Table 17-5. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter SCK cycle time Symbol tKCY tKH, tKL tSIK tKSI tKSO tINTH, tINTL tRSL Conditions External SCK source Internal SCK source SCK high, low width SI setup time to SCK high SI hold time to SCK high Output delay for SCK to SO Interrupt input, high, low width RESET input low width External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source External SCK source Internal SCK source All interrupt VDD = 3 V Input VDD = 3 V 500 2,000 700 - Min 1,000 1,000 500 tKCY/2-50 250 250 400 400 - - 300 250 - - ns ns Typ - Max - Unit ns Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF
17-7
ELECTRICAL DATA
S3C821A/P821A
Table 17-6. A/D Converter Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy VDD = 5.12 V AVREF = 5.12 V AVSS = 0 V Conversion time (1) Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current tCON VIAN RAN AVREF AVSS IADIN 8 bit conversion 34 x n/fxx (2), n=1,4,8,16 - - - - AVREF = VDD = 5V 17 AVSS 2 2.5 VSS - - - 1,000 - - - 170 AVREF - VDD VSS + 0.3 10 s V M V V A Symbol Conditions Min - - Typ 8 - Max - 2 Unit bit LSB
NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. fxx is a selected system clock for peripheral hardware.
17-8
S3C821A/P821A
ELECTRICAL DATA
t INTL
t INTH
0.8 V DD 0.2 V DD
NOTE: The unit t CPU means one CPU clock period.
Figure 17-3. Input Timing for External Interrupts
t RSL RESET 0.2 V DD
Figure 17-4. Input Timing for RESET
t KCY t KL SCK t KH 0.8 V DD 0.2 V DD t SIK t KSI 0.8 V DD 0.2 V DD
SI
INPUT DATA
t KSO SO OUTPUT DATA
Figure 17-5. Serial Data Transfer Timing
17-9
ELECTRICAL DATA
S3C821A/P821A
Table 17-7. Main System Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Crystal Clock Circuit
C1
Parameter Main oscillation frequency
Condition (VDD) 2.2 V-5.5 V
Min 0.4
Typ -
Max 8
Unit MHz
XIN XOUT
C2
2.0 V-5.5 V Ceramic
C1
0.4 0.4
- -
6 8
XIN XOUT
Main oscillation frequency
2.2 V-5.5 V
C2
2.0 V-5.5 V External clock
XIN XOUT
0.4 0.4
- -
6 8
XIN input frequency
2.2 V-5.5 V
2.0 V-5.5 V RC
XIN R XOUT
0.4 0.4
- -
6 2
Frequency
3.0 V
Table 17-8. Subsystem Oscillation Characteristics (TA = - 40 C + 85 C) Oscillator Crystal Clock Circuit
C1
Parameter Sub oscillation frequency
Condition (VDD) 2.0 V-5.5 V
Min 32
Typ 32.768
Max 35
Unit kHz
XTIN XTOUT
C2
External clock
XTIN XTOUT
XTIN input frequency
2.0 V-5.5 V
32
-
500
kHz
17-10
S3C821A/P821A
ELECTRICAL DATA
Table 17-9. Main Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal Ceramic External clock fx > 400 kHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. XIN input High and Low width (tXH, tXL) Test Condition Min - - 25 Typ - - - Max 20 10 500 Unit ms ms ns
1/fx t XL t XH
XIN
VDD - 0.1 V 0.1 V
Figure 17-6. Clock Timing Measurement at XIN
Table 17-10. Sub Oscillation Stabilization Time (TA = - 40 C + 85 C, VDD = 2.0 V to 5.5 V) Oscillator Crystal External clock Test Condition - XTIN input High and Low width (tXH, tXL) Min - 1 Typ - - Max 10 18 Unit s s
1 / f xt t XTL t XTH
XTIN
VDD - 0.1 V 0.1 V
Figure 17-7. Clock Timing Measurement at XTIN
17-11
ELECTRICAL DATA
S3C821A/P821A
INSTRUCTION CLOCK 1.33 MHz
f x(Main oscillation frequency) 8 MHz
1.00 MHz
6 MHz
8.33 kHz
400 kHz
1
2 2.2
3
4
5 5.5
6
7
SUPPLY VOLTAGE (V) INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)
Figure 17-8. Operating Voltage Range
17-12
S3C821A/P821A
MECHANICAL DATA
18
OVERVIEW
MECHANICAL DATA
The S3C821A microcontroller is currently available in 80-pin QFP and TQFP package.
23.90 0.3 20.00 0.2 0-8 0.15
+0.10 - 0.05
17.90 0.3
14.00 0.2
0.10 MAX 0.80 0.20 (1.00) 0.05 MIN 2.65 0.10 3.00 MAX (0.80) 0.80 0.20
80-QFP-1420C
#80
#1 0.80 0.35 0.1 0.15 MAX
NOTE: Dimensions are in millimeters.
Figure 18-1. 80-Pin QFP Package Demensions
18-1
MECHANICAL DATA
S3C821A/P821A
14.00BSC 12.00BSC 0- 7 0.09-0.20
14.00BSC
80-TQFP-1212
#80
#1 0.50 0.17-0.27 0.08 MAX M (1.25)
NOTE: Dimensions are in millimeters.
Figure 18-2. 80-Pin TQFP Package Demensions
18-2
0.60 0.15 0.05-0.15 1.00 0.05 1.20 MAX
12.00BSC
S3C821A/P821A
S3P821A OTP
20
OVERVIEW
S3P821A OTP
The S3P821A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C821A microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P821A is fully compatible with the S3C821A, both in function and in pin configuration. Because of its simple programming requirements, the S3P821A is ideal as an evaluation chip for the S3C821A.
20-1
S3P821A OTP
S3C821A/P821A
P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 SDAT/P2.0/AS SCLK/P2.1/DR VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P1.0/SEG24/AD0 P0.7/SEG23/A15 P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5
S3P821A
(80-TQFP)
SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11
Figure 20-1. S3P821A Pin Assignments (80-TQFP-1212 Package)
20-2
P2.5/INT1/T1CK P2.6/INT2/TA P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8 P4.5/INT9 P4.6/INT10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S3C821A/P821A
S3P821A OTP
P0.7/SEG23/A15 P1.0/SEG24/AD0 P1.1/SEG25/AD1 P1.2/SEG26/AD2 P1.3/SEG27/AD3 P1.4/SEG28/AD4 P1.5/SEG29/AD5 P1.6/SEG30/AD6 P1.7/SEG31/AD7 SDAT/P2.0/AS SCLK/P2.1/DR VDD1/VDD1 VSS1/VSS1 XOUT XIN VPP/TEST XTIN XTOUT RESET/RESET RESET P2.2/DW P2.3/DM P2.4/INT0/T0CK P2.5/INT1/T1CK P2.6/INT2/TA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P0.6/SEG22/A14 P0.5/SEG21/A13 P0.4/SEG20/A12 P0.3/SEG19/A11 P0.2/SEG18/A10 P0.1/SEG17/A9 P0.0/SEG16/A8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7
S3P821A
(80-QFP)
SEG6 SEG5 SEG4 SEG3/COM7 SEG2/COM6 SEG1/COM5 SEG0/COM4 COM3 COM2 COM1 COM0 VDD2 (EXT) VSS2 VLC1 P5.6 P5.5 P5.4 P5.3/BUZ P5.2/SO P5.1/SI P5.0/SCK P4.7/INT11 P4.6/INT10 P4.5/INT9
Figure 20-2. S3P821A Pin Assignments (80-QFP-1420C Package)
P2.7/INT3/TB AVREF P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 AVSS P3.4 P3.5 P3.6 P3.7/T0/T0PWM/T0CAP P4.0/INT4 P4.1/INT5 P4.2/INT6 P4.3/INT7 P4.4/INT8
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20-3
S3P821A OTP
S3C821A/P821A
Table 20-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P2.0 Pin Name SDAT Pin No. 8 (10) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip Initialization Logic power supply pin. VDD should be tied to + 5 V during programming.
P2.1 VPP
SCLK TEST
9 (11) 14 (16)
I/O I
RESET VDD1/VSS1
RESET VDD1/VSS1
17 (19) 10 (12)/11 (13)
I -
NOTE: ( ) means 80 QFP package.
Table 20-2. Comparison of S3P821A and S3C821A Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P821A 48-K byte EPROM 2.0 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 80 QFP/80 TQFP User Program 1 time 80 QFP/80 TQFP Programmed at the factory S3C821A 48-K byte mask ROM 2.0 V to 5.5 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P821A, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 20-3 below. Table 20-3. Operating Mode Selection Criteria VDD 5V
VPP
(TEST) 5V 12.5 V 12.5 V 12.5 V
REG/ MEM 0 0 0 1
ADDRESS
R/W 1 0 1 0 EPROM read
MODE
(A15-A0) 0000H 0000H 0000H 0E3FH
EPROM program EPROM verify EPROM read protection
NOTE: "0" means Low level; "1" means High level.
20-4
S3C821A/P821A
S3P821A OTP
Table 20-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Operating Voltage Symbol VDD Conditions f OSC = 8 MHz (Instruction clock = 1.33 MHz) f OSC = 6 MHz (Instruction clock = 1 MHz) P0 and P1 RESET, P2, P3, P4, and P5 XIN, XTIN P0 and P1 RESET, P2, P3, P4, and P5 XIN, XTIN VDD = 3 V; IOH = - 200 A All output pins VDD = 3 V; IOL= 1 mA All output pins VIN = VDD All input pins except those specified below for ILIH2 VIN = VDD XIN, XOUT, XTIN, and XTOUT VIN = 0 V All input pins except those specified below for ILIL2 and RESET VIN = 0 V XIN, XOUT, XTIN, and XTOUT VOUT = VDD All output pins VOUT = 0 V All output pins VDD = 2.7 V to 5.5 V - 15 A per common pin VLCD = 2.7 V to 5.5 V - 15 A per segment pin - - - - - - - - VDD - 1.0 - - - 0.4 - Min 2.2 2.0 0.7 VDD 0.8 VDD VDD - 0.1 0 - - VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 - 1.0 1 A V Typ - Max 5.5 Unit V
Input High voltage
VIH1 VIH2 VIH3
Input Low voltage
VIL1 VIL2 VIL3
Output High voltage Output Low voltage Input High leakage current
VOH VOL ILIH1
ILIH2 Input Low leakage current ILIL1
20 -1
ILIL2 Output High leakage current Output Low leakage current |VDD-COMi| voltage drop (i = 0-7) |VDD-SEGx| voltage drop (x = 0-31) ILOH ILOL VDC
- 20 1 -1 120 mV
VDS
-
-
120
20-5
S3P821A OTP
S3C821A/P821A
Table 20-4. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter VLC2 output voltage VLC3 output voltage VLC4 output voltage VLC5 output voltage Pull-up resistors Symbol VLC2 VLC3 VLC4 VLC5 RL1 RL2 VIN = 0 V; TA = 25C VDD = 3.0 10%; Ports 0-5 VIN = 0 V; TA = 25 C VDD = 3.0 10 % Conditions VDD = 2.7 V to 5.5 V LCD clock = 0 Hz VLC1 = VDD Min 0.8 VDD - 0.15 0.6 VDD - 0.15 0.4 VDD - 0.15 0.2 VDD - 0.15 30 300 Typ 0.8 VDD 0.6 VDD 0.4 VDD 0.2 VDD 80 500 Max 0.8 VDD + 0.15 0.6 VDD + 0.15 0.4 VDD + 0.15 0.2 VDD + 0.15 200 800 Unit V
k
LCD voltage dividing resistor Supply current
(note)
RLCD IDD1
RESET only VLCD = 2.7 V to 5.5 V TA = 25 C Run mode; VDD=5.0V10% Crystal oscillator C1 = C2 = 22 pF VDD = 3.0 V 10 % 6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz
45 -
65 6.0 4.5 2.9 2.0 1.3 1.2 0.6 0.4 20 7 0.5 0.3
80 12 9.0 5.8 4.0 2.6 2.4 1.2 0.8 40 14 3 2
k mA
IDD2
Idle mode; VDD=5.0 V 0% Crystal oscillator C1 = C2 = 22 pF VDD = 3.0 V 10 %
6.0 MHz 4.19 MHz 6.0 MHz 4.19 MHz
IDD3 IDD4 IDD5
Run mode; VDD = 3.0 V 10 % 32 kHz crystal oscillator Idle mode; VDD = 3.0 V 10 % 32 kHz crystal oscillator Stop mode; VDD = 5.0 V 10 % Stop mode; VDD = 3.0 V 10 %
A
NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and IDD2 include power consumption for subsystem clock oscillation. 3. IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used. 4. IDD5 is current when main system clock and subsystem clock oscillation stops.
20-6
S3C821A/P821A
S3P821A OTP
INSTRUCTION CLOCK 1.33 MHz
f x(Main oscillation frequency) 8 MHz
1.00 MHz
6 MHz
8.33 kHz
400 kHz
1
2 2.2
3
4
5 5.5
6
7
SUPPLY VOLTAGE (V) INSTRUCTION CLOCK = 1/6n x oscillator frequency (n = 1, 2, 8, 16)
Figure 20-3. Operating Voltage Range
20-7

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